1. Field of the Invention
The present invention relates to a zero signal state detecting circuit for an optical receiver used in an optical digital transmission system, and more particularly, to a detecting circuit for detecting a zero signal state and preventing an operation error caused by a noise component of the signal.
2. Description of the Prior Art
A photo detecting circuit having an avalanche photodiode has been utilized for an optical receiver or optical repeater in an optical digital transmission system. The multiplication factor of the photodetecting circuit is controlled by an automatic gain control circuit to detect a received optical signal level. When an optical signal is not detected, the multiplication factor of the photodetecting circuit becomes large and the amplitude of the noise component becomes large. As a result, an error signal is received or repeated as if an optical signal were detected. In order to resolve the above problem, it is necessary to detect a zero signal state and stop the operation of the repeater or receiver.
One method for detecting a zero signal state is at the stage where a timing signal is extracted from the received signal and a transmission signal is regenerated. Such a zero signal state detecting circuit is disclosed in Japanese Patent Publication (Kokai) No. 57-133734, and the circuit disclosed therein is attached as FIG. 1. The zero signal state detecting circuit is utilized in an optical repeater having a timing clock extracting circuit. The timing circuit has a band pass filter 11, a tuning amplifier 12 and a differential type limiting amplifier 14. In the zero signal state detecting circuit, a zero signal state is detected by taking two differential output signals from the differential type limiting amplifier 15 and applying them to a zero signal state detecting circuit 16. A first of the differential output signals is provided to the base of a first transistor Q.sub.11. The emitter of the first transistor is connected through first resistor R.sub.11 for shifting the voltage level to a first constant-current generator comprised of second transistor Q.sub.13 and second resistor R.sub.13. The second of the differential output signals is provided to the base of third transistor Q.sub.12. The emitter of the third transistor Q.sub.12 is connected through third resistor R.sub.12 to a second constant-current generator comprised of fourth transistor Q.sub.14 and fourth resistor R.sub.14.
The first of the differential output signals, voltage level-shifted by the first resistor, R.sub.11 and the second of the differential output signals, taken at a point between the emitter and resistance R.sub.12 so as not to be voltage level shifted, are applied to two input terminals of a first comparator 4. In the first comparator 4, an enlarged level difference is detected even if the difference of the amplitude between the received signal state and the zero signal state is small. The output of the first comparator 4 is provided to a peak detecting circuit 5, and the output of the peak detecting circuit is sent to a second comparator 6. The second comparator detects a zero signal state.
As mentioned above the first of the differential outputs from the limiting amplifier 14 is level-shifted by the first resistor. The level shifting voltage is controlled by varying the resistor value.
However, both collector currents of the first and third transistors Q.sub.11 and Q.sub.12 are unbalanced, so that the temperature characteristic of the level shifting voltage is not good. As a result, a zero signal state is not always correctly detected.